
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RAM_ctrl is
    port(
         clk: in std_logic;
         rst: in std_logic;
	 		YW: in std_logic_vector(8 downto 0);
	 		ZW: in std_logic_vector(8 downto 0);
			output: out std_logic;
			a_write: out integer range 103040 downto 0
   	);
end RAM_ctrl;

architecture Behavioral of RAM_ctrl is

begin
	process(clk)
		variable reg: std_logic:='0';
		variable cnt: integer:=0;
	begin
		if rising_edge(clk) then
			output<='1';
			if reg='0' then
				if rst='1' then
					reg:='1';
					cnt:=0;
					a_write <= cnt;
					output <='0';
				else
					a_write<=conv_integer((("000000000")&YW)+(("000000000")&ZW)+('0'&ZW&("00000000"))+(("000")&ZW&("000000")));
				end if;
			elsif cnt=103040 then
				reg:='0';
				a_write<=conv_integer((("000000000")&YW)+(("000000000")&ZW)+('0'&ZW&("00000000"))+(("000")&ZW&("000000")));
			else
				cnt:=cnt+1;
				a_write <= cnt;
				output <='0';
			end if;
		end if;	
	end process;		
end Behavioral;

